Research focus
About the research
How can programmable accelerators and chip-level interconnection networks be designed to improve performance and energy efficiency of future computer systems?
Read the full research overview
The research group builds prototype systems and tape-out class projects that implement digital ASIC accelerators and mixed digital/analog chips to validate design assumptions and test hardware-software integration. Researchers develop parallel programming frameworks and software-managed scratchpad memory techniques to support dynamic task parallelism and efficient use of manycore architectures. The group explores productive VLSI chip design methodologies and generator-checking techniques for dynamic hardware description languages to improve reliability and correctness of hardware generators. The lab evaluates programmable accelerator architectures and eFPGA integration for cache-coherent SoCs to study scalable accelerator-software interfaces.
Selected publications
2 listedCIFER: A Cache-Coherent 12nm 16mm2 SoC with Four 64-bit RISC-V Application Cores, 18 32-bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA
IEEE Solid-State Circuits Letters (SSCL)
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs
6th ACM/IEEE Int’l Symp. on Machine Learning for CAD (MLCAD)
People & alumni
Team details haven’t been added. See the lab’s website for its current members.
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Sources & listing information
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